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MiSTer Updates & Changelog • Re: MiSTer updates and changelog


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- implement 3 different turbo speeds
- Move datacache into CPU -> speedup when using turbo setting "high"

- fixed memory card loading edge case leading to memory card data not being available
- fixed wrong savestate slot index when loading core
- fixed edge case where loading a savestate would hang up the core until reset is triggered
- fixed CPU blockLoadforward edge case (CPU test from pcsx-redux is now pass)
- many cleanups and resource reductions, FPGA logic went from 97% to 93%

accuracy improvements:
- Memory: CD register bus is now using extbus logic
- Memory: extbus timing modified when using PStrobe together with RecP(CD timings)
- Memory: adjust timings for BIOS reads
- Memory: rework sdram -> instruction cache interface, reducing cache fetch time by 1 cycle, fulfilling test against hardware
- CPU: implement out-of-order load pipelining
- CPU: implement readback of CACHECONTROL register
- CPU: make instruction fetch stage fully independent of data fetch stage
- DMA: add timing cost for ram page switch and refresh
- DMA: reduce initial overhead by 2 cycles
- Timer: implement non-retrigger mode by using Mode bit 6

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